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ap0101cs hdr: image signal processor (isp) features ap0101cs/d rev. 7, 1/16 en 1 ?semiconductor components industries, llc 2016, ap0101cs high-dynamic range (hdr) image signal processor (isp) ap0101cs datasheet, rev. 7 for the latest product datasheet, please visit www.onsemi.com features ? supports on semiconductor sensors with up to 1.2 mp (1280x960) ? 45 fps at 1.2 mp, 60 fps at 720p ? optimized for operation with hdr sensors ? color and gamma correction ? auto exposure, auto white balance, 50/60 hz flicker avoidance ? adaptive local tone mapping (altm) ? test pattern generator ? two-wire serial programming interface ? interface to low-cost flash or eprom through spi bus (to configure and load patches) ? high-level host command interface ? standalone operation supported ? up to 5 gpio ?fail-safe io ? multi-camera synchronization support ?dual band ir filter support applications ? smpte296 hdcctv cameras ? surveillance network ip cameras notes: 1. 20-bit in one pixel clock format is only available in smpte mode with the use of 4 gpios. 2. with input clock below 10 mhz, the two wire serial interface is supported only up to 100 khz 3. maximum frame rate depends on output inter- face and data format configuration used. 4. 720p hdr 60 fps 74.25 mhz ycbcr_422_16 table 1: key performance parameters parameter value primary camera interface parallel primary camera input format raw12 linear/companded bayer data output interface up to 20-bit parallel 1 output format yuv422 8-bit,10-bit, and smpte296m 10-, 12-bit tone-mapped bayer maximum resolution 1280x960 (1.2 mp) input clock range 2 6-30 mhz maximum frame rate 3 45 fps at 1.2 mp, 60 fps at 720p maximum output clock frequency parallel clock up to 84 mhz supply voltage v dd io_s 1.8 or 2.8 v nominal v dd io_h 2.5 or 3.3 v nominal v dd _reg 1.8v nominal v dd io_otpm 2.5 or 3.3 v nominal operating temperature (ambient - t a ) C30c to +70c typical power consumption 4 130 mw
ap0101cs/d rev. 7, 1/16 en 2 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. fo r reference documenta- tion, including information on evaluation kits, please visi t our web site at www.onsemi.com. table 2: available part numbers part number product description orderable product attribute description ap0101cs2l00spga0-dr1 1mp co-processor, 100-ball vfbga drypack AP0101CS2L00SPGAD3-GEVK ap0101cs demo kit ap0101cs2l00spgah-gevb ap0101cs head board
ap0101cs/d rev. 7, 1/16 en 3 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 multi-camera synchronization support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 image flow processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 camera control and auto functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 ae track driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 auto white balance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 dual band ircf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 exposure and white balance modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 flicker avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 output formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 sensor embedded data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 slave two-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 usage modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 host command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 package and die options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
ap0101cs/d rev. 7, 1/16 en 4 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) general description general description the on semiconductor ap0101cs is a high -performance, ultra-low power in-line, digital image processor optimized for use with high dynamic range (hdr) sensors. the ap0101cs provides full auto-functions supp ort (awb and ae) and adaptive local tone mapping (altm) to enhance hdr images an d advanced noise reduction which enables excellent low-light performance. functional overview figure 1 shows the typical configuration of the ap0101cs in a camera system. on the host side, a two-wire serial interface is us ed to control the operation of the ap0101cs, and image data is transferred using the para llel bus between the ap0101cs and the host. the ap0101cs interface to the sensor also uses a parallel interface. figure 1: ap0101cs connectivity system interfaces figure 2 on page 5 shows typical ap0101cs device connections. all power supply rails must be decoupled fr om ground using capacitors as close as possible to the package. the ap0101cs signals to the sensor and host in terfaces can be at different supply voltage levels to optimize power consumption and maximize flexibility. table 4 on page 7 provides the signal descriptions for the ap0101cs. 1.2mp hdr sensor 12-bit parallel host up to 20-bit parallel two-wire serial i/f (master) two-wire serial if (slave)
ap0101cs/d rev. 7, 1/16 en 5 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces figure 2: typical configuration notes: 1. this typical configuration shows only one scenar io out of multiple possibl e variations for this sen- sor. 2. on semiconductor recommends a 1.5k ?? resistor value for the two-wire serial interface r pull - up ; however, greater values may be us ed for slower transmission speed. 3. reset_bar has an internal pull-up resistor and can be left floating if not used. 4. the decoupling capacitors for the regulator input and output should have a value of 1.0uf. the capacitors should be ceramic and need to have x5r or x7r dielectric. 5. trst_bar connects to gnd for normal operation. 6. on semiconductor recommends that 0.1 ? f and 1 ? f decoupling capacitors for each power supply are mounted as close as possible to the pin. actual values an d numbers may vary depending on lay- out and design consideration v dd io_otpm ldo_op 4 v dd _reg 4 v dd io_s 6 v dd io _s v dd io _h s ensor io power host io power m_s clk m_ s data extclk_out reset_bar_out fv_in lv_in pixclk_in din [11:0] trigger_out v dd _reg fb_sense ldo_op v dd _pll 1.8v (regulator ip) v dd 1.2v ( r egulator op) p ower up c ore and pll gnd_reg fv_out lv_out pixclk_out d out [1 5:0] s clk s data s addr extclk xtal spi_cs_bar spi_clk spi_sdo spi_sdi gpio_1 trst_bar 5 v dd io_otpm otpm power v dd io_h 6 gnd r pull-up 2 r pull-up 2 reset_bar 3 gpio_2 gpio_3 gpio_4 gpio_5 frame_sync standby oscillator
ap0101cs/d rev. 7, 1/16 en 6 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces the following table summarizes the key signals when using the internal regulator. (the internal regulator has to be used for ap0101at.) table 3: key signals when using the regulator signal name internal regulator v dd _reg 1.8v fb_sense 1.2v (input) ldo_op 1.2v (output)
ap0101cs/d rev. 7, 1/16 en 7 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces crystal usage as an alternative to using an external os cillator, a crystal may be connected between extclk and xtal. two small loading capacitors and a feedback resistor should be added, as shown in figure 3. figure 3: using a crystal inst ead of an external oscillator rf represents the feedback resistor, an rf value of 1m ? would be sufficient for ap0101cs. c1 and c2 are decided according to the crystal or resonator cl specification. in the steady state of oscillation, cl is defined as (c1 x c2)/(c1+c2). in fact, the i/o ports, the bond pad, package pin and pcb traces all contribute the parasitic capacitance to c1 and c2. therefore, cl can be rewritten to be (c1* x c2*)/(c1*+c2*), where c1*=(c1+cin, stray) and c2*=(c2+cout, stray). the stray ca pacitance for the io ports, bond pad and package pin are known which means the formulas can be rewritten as c1*=(c1+1.5pf+cin, pcb) and c2*=(c2+1.3pf+cout, pcb). table 4: pin descriptions name type description extclk input master input clock. this can either be a square-wave generated from an oscillator (in which case the xtal input must be left unco nnected) or direct conne ction to a crystal. xtal output if extclk is connected to one pin of a crystal , the other pin of the crystal is connected to xtal pin; otherwise this sign al must be left unconnected. reset_bar input/pu master reset signal, active low. this signal has an internal pull up. s clk input two-wire serial interface clock (host interface). s data i/o two-wire serial interfac e data (host interface). s addr input selects device address for the two-wire slav e serial interface. when connected to gnd the device id is 0x90. when wired to v dd io_h, a device id of 0xba is selected. frame_sync input this input can be used to set the output timi ng of the ap0101cs. this signal should be connected to gnd if not used. standby input standby mode control, active high. spi_s clk output clock output for interfacing to an external spi flash or eeprom memory. extclk xtal ap0101 c1 c2 rf=1m
ap0101cs/d rev. 7, 1/16 en 8 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces spi_sdi input data in from spi flash or eeprom memory. when no spi device is fitted, this signal is used to determine whether the ap 0101cs should auto-configure: 0: do not auto-configure; two-wire interface will be used to configure the device (host- config mode) 1: auto-configure. this signal has an internal pull-up resistor. spi_sdo output data out to spi flash or eeprom memory. spi_cs_bar output chip select out to spi flash or eeprom memory. fv_out output host frame valid output (s ynchronous to pixclk_out) lv_out output host line valid output (s ynchronous to pixclk_out) pixclk_out output host pixel clock output. d out [15:0] output host pixel data output (s ynchronous to pixclk_out) d out [15:0]. note 20-bit output (smpte) also uses gpio[5:2]. gpio [5:1] i/o general purpose digital i/o. note: 20-bit output (smpte) also uses gpio[5:2] trst_bar input must be tied to gnd in normal operation. ext_clk_out output clock to external sensor. reset_bar_out output reset signal to external sensor. m_s clk output two-wire serial interface clock (master). m_s data i/o two-wire serial interface clock (master). fv_in input sensor frame valid input. lv_in input sensor line valid input. pixclk_in input sensor pixel clock input. din[11:0] input sensor pixel data input d in [11:0] trigger_out output trigger signal for external sensor. v dd io_s supply sensor i/o power supply. gnd supply ground for sensor io, host io, pll, v dd io_otpm, and v dd . v dd _reg supply input to on-chip 1.8v to 1.2v regulator. ldo_op output output from on-chip 1.8v to 1.2v regulator. note: the regulator on the ap0101cs must be used. fb_sense input on-chip regulator sense signal. gnd_reg supply ground for on-chip regulator v dd _pll supply pll supply. v dd supply core supply. v dd io_otpm supply otpm power supply. v dd io_h supply host i/o power supply. table 4: pin descriptions (continued) name type description
ap0101cs/d rev. 7, 1/16 en 9 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces power-up and down sequence powering up and down the ap0101cs requires voltages to be applied in a particular order, as seen in figure 4. the timing requirements are shown in table 6. the ap0101cs includes a power-on reset feature that init iates a reset upon power up of the ap0101cs. figure 4: power-up and power-down sequence table 5: package pinout 1 2 3 4 5 6 7 8 9 a extclk xtal s clk spi_sdo d out [15] d out [13] d out [10] d out [9] d out [8] b v dd v dd io_h s data spi_sdi d out [14] d out [12] d out [11] d out [7] d out [6] c ext_clk_out v dd io_s s addr spi_cs_ba r gnd pixclk_out fv_out d out [5] d out [4] d reset_bar_out v dd gnd spi_sclk gnd trst_bar lv_out d out [3] d out [2] e d in [3] d in [7] gnd fb_sense gnd gnd v dd _pll d out [1] d out [0] f d in [11] d in [2] ldo_op gnd_reg gnd gnd v dd _pll v dd _pll v dd io_otpm g d in [6] d in [1] d in [4] v dd _reg v dd io_s v dd reset_bar gpio[4] gpio[5] h d in [10] d in [0] d in [8] fv_in m_s data v dd io_h frame_sync gpio[2] gpio[3] j d in [5] d in [9] pixclk_in lv_in m_s clk v dd standby trigger_out gpio[1] v dd io_h v dd _reg t3 t5 extclk s clk t4 s data t1 t2 t7 t6 v dd io_s, v dd io_otpm dv/dt dv/dt dv/dt reset
ap0101cs/d rev. 7, 1/16 en 10 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces note: if the system cannot support th is power supply slew rate, then power supplies must be designed to overcome inrush currents in table 24, inrush current, on page 38. reset the ap0101cs has 3 types of reset available: ? a hard reset is issued by toggling the reset_bar signal ? a soft reset is issued by writing comman ds through the two-wire serial interface ? an internal power-on reset table 7 shows the output states when the part is in various states. table 6: power-up and power-down signal timing symbol parameter min typ max unit t1 delay from v ddio _h to v dd io_s, v dd io_otpm 0 C 50 ms t2 delay from v dd io_h to v dd _reg 0 C 50 ms t3 extclk activation t2 + 1 C C ms t4 first serial command 100 C C extclk cycles t5 extclk cutoff t6 C C ms t6 delay from v dd _reg to v dd io_h 0 C 50 ms t7 delay from v dd io_s, v dd io_otpm to v dd io_h 0 C 50 ms dv/dt power supply ramp time (slew rate) C C 0.1 v/ ? s table 7: output states name hardware states firmware states notes reset state default state hard standby soft standby streaming idle extclk (clock running or stopped) (clock running) (clock running or stopped) (clock running) (clock running) (clock running) input xtal n/a n/a n/a n/a n/a n/a input reset_bar (asserted) (negated) (negat ed) (negated) (negated) (negated) input s clk n/a n/a (clock running or stopped) (clock running or stopped) (clock running or stopped) (clock running or stopped) input. must always be driven to a valid logic level s data high- impedance high- impedance high- impedance high- impedance high- impedance high- impedance input/output. a valid logic level should be established by pull- up s addr n/a n/a n/a n/a n/a n/a input. must always be driven to a valid logic level frame_sync n/a n/a n/a n/a n/a n/a input. must always be driven to a valid logic level standby n/a (negated) (asserted) (negated) (negated) (negated) input. must always be driven to a valid logic level
ap0101cs/d rev. 7, 1/16 en 11 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces spi_sclk high- impedance driven, logic 0 driven, logic 0 driven, logic 0 output spi_sdi internal pull- up enabled internal pull- up enabled internal pull- up enabled internal pull- up enabled input. internal pull- up permanently enabled. spi_sdo high- impedance driven, logic 0 driven, logic 0 driven, logic 0 output spi_cs_bar high- impedance driven, logic 1 driven, logic 1 driven, logic 1 output ext_clk_out driven, logic 0 driven, logic 0 driven, logic 0 driven, logic 0 output reset_bar_o ut driven, logic 0 driven, logic 0 driven, logic 1 driven, logic 1 output. firmware will release sensor reset m_s clk high- impedance high- impedance high- impedance high- impedance input/output. a valid logic level should be established by pull- up m_s data high- impedance high- impedance high- impedance high- impedance input/output. a valid logic level should be established by pull- up fv_in ,lv_in, pixclk_in, din[11:0] n/a n/a n/a n/a n/a input. must always be driven to a valid logic level fv_out, lv_out, pixclk_out, dout[15:0] high- impedance varied driven if used driven if used driven if used driven if used output. default state dependent on configuration gpio[5:2] high- impedance input, then high- impedance driven if used driven if used driven if used driven if used input/output. after reset these pins are sampled as inputs as part of auto- configuration. gpio1 high- impedance high- impedance high- impedance high- impedance high- impedance high- impedance trigger_out high- impedance high- impedance driven if used driven if used driven if used driven if used trst_bar n/a n/a (negated) (ne gated) (negated) (negated) input. must always be driven to a valid logic level. table 7: output states name hardware states firmware states notes reset state default state hard standby soft standby streaming idle
ap0101cs/d rev. 7, 1/16 en 12 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces hard reset the ap0101cs enters the reset state when th e external reset_bar signal is asserted low, as shown in figure 5. all the output signals will be in high-z state. figure 5: hard reset operation note: this assumes auto-config. soft reset a soft reset sequence to the ap0101cs can be activated by writing to a register through the two-wire serial interface. hard standby mode the ap0101cs can enter hard standby mode by using the external standby signal, as shown in figure 6. entering standby mode 1. assert standby signal high. exiting standby mode 1. de-assert standby signal low. table 8: hard reset symbol definition min typ max unit t 1 reset_bar pulse width 50 C C extclk cycles t 2 active extclk required af ter reset_bar asserted 10 C C t 3 active extclk required before reset_bar de- asserted 10 C C t 4 first two-wire serial interface communication after reset_bar is high 100 C C extclk reset reset_bar mode t 2 t 3 t 1 internal initialization time s data enter streaming mode t 4 all outputs data active data active
ap0101cs/d rev. 7, 1/16 en 13 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) system interfaces figure 6: hard standby operation table 9: hard standby signal timing symbol parameter min typ max unit t 1 standby entry complete C C 2 frames lines t 2 active extclk required after going into standby mode 10 C C extclks t 3 active extclk required before standby de-asserted 10 C C extclks extclk standby standby asserted t 1 standby mode extclk disabled t 2 t 3 extclk enabled mode
ap0101cs/d rev. 7, 1/16 en 14 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) multi-camera synchronization support multi-camera synchronization support the ap0101cs supports multi-camera synchronization via the frame_sync pin. the host (or controlling entity) 'broadcasts' a sy nc-pulse to all cameras within the system that triggers streaming start. the ap0101cs will propagate the signal to the trig- ger_out pin to the sensor's trigger pin. the ap0101cssupports two different trigger mo des. the first mode supported is 'single- shot'; this is when the trigger pulse will cause one frame to be output from the image sensor and ap0101cs (see figure 7). figure 7: single-shot mode table 10: tr igger timing parameter name conditions min typ max unit frame_sync to fv_out t frmsync_fvh 8 lines+ exposure time + sensor delay C C lines frame_sync to trigger_out t trigger_prop C C 9 ns t frame_sync t framesync 3 C C extclk cycles ?
ap0101cs/d rev. 7, 1/16 en 15 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) image flow processor the second mode supported is called 'continuous'; this is when a trigger pulse will cause the part to continuously output frames, se e figure 8. this mode would be especially useful for applications which have multiple sensors and need to have their video streams synchronized (for example, surroun d view or panoramic view applications). figure 8: continuous mode note: this diagram is not to scale. when two or more cameras have a signal a pplied to the frame_sync input at the same time, the respective fv_out signals would be synchronized within 5 pixclk_out cycles. this assumes th at all cameras have the same conf iguration settings and that the exposure time is the same. image flow processor image and color processing in the ap0101cs is implemented as an image flow processor (ifp) coded in hardware logic. during norm al operation, the embedded microcontroller will automatically adjust the operating parameters. for normal operation of the ap0101cs, a stream of raw image data from th e attached image sensor is fed into the color pipeline. the user also has the option to select a number of test patterns to be input instead of sensor data. the test pattern is fed to the ifp for testing the image pipe- line without sensor operation. the test patterns can be selected by programm ing variables. to select enter test pattern mode, set r0xc88f to 0x02 and issue a change - config request; to exit this mode, set r0xc88f to 0x00. frame_sync trigger_out fv_out
ap0101cs/d rev. 7, 1/16 en 16 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) image flow processor figure 9: ap0101cs ifp linear or com panded data defect correction , noise reduction rx decompanding black level subtraction , d igital gain control pga , raw 12- or 20-bit bayer ae, fd and altm stats 12-bit altm bayer color interpolation altm color correction aperture correction gamma rgb2yuv aw b stats color kill yuv filters scaler crop progressive test pattern generator raw bayer altm bayer rgb ycbcr progressive parallel or smpte (ycbcr or bayer)
ap0101cs/d rev. 7, 1/16 en 17 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) image flow processor test patterns figure 10: color bar test pattern test pattern example flat field field_wr= cam_mode_select, 0x02 field_wr= cam_mode_test_pattern_select, 0x01 field_wr= cam_mode_test_pattern_red, 0x000fffff field_wr= cam_mode_test_pattern_green, 0x000fffff field_wr= cam_mode_test_pattern_blue, 0x000fffff load = change-config changing the values in r0xc890-r0xc898 will change the color of the test pattern. 100% color bar field_wr= cam_mode_select, 0x02 field_wr= cam_mode_test_pattern_select, 0x02 load = change-config pseudo-random field_wr= cam_mode_select, 0x02 field_wr= cam_mode_test_pattern_select, 0x05 load = change-confi g linear ramp field_wr= cam_mode_select, 0x02 field_wr= cam_mode_test_pattern_select, 0x09 load = change-config fade-to-gray field_wr= cam_mode_select, 0x02 field_wr= cam_mode_test_pattern_select, 0x08 load = change-config
ap0101cs/d rev. 7, 1/16 en 18 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) image flow processor defect correction after data decompanding the image stream processing star ts with defect correction. to obtain defect free images, the pixels marked defective during sensor readout and the pixels determined defective by the defect co rrection algorithms are replaced with values derived from the non-defectiv e neighboring pixels. this image processing technique is called defect correction. adacd (adaptive color difference) automotive applications require good performance in extremely low light, even at high temperature conditions. in these stringent conditions the image sensor is prone to higher noise levels, and so efficient noise reduction techniques are required to circum- vent this sensor limitation and deliver a high quality image to the user. the adacd noise reduction filter is able to adapt its noise filtering process to local image structure and noise level, removing most objectionable color noise while preserving edge details. black level subtracti on and digital gain after noise reduction, the pixel data goes th rough black level subtra ction and multiplica- tion of all pixel values by a programmable di gital gain. independent color channel digital gain can be adjusted with registers. black le vel subtract (to compensate for sensor data pedestal) is a single value applied to all co lor channels. if the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0. positional gain adjustments (pga) lenses tend to produce images whose brightness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative re sult of all these factors is known as image shading. the ap0101cs has an embedded sh ading correction module that can be programmed to counter the shading effects on each individual r, gb, gr, and b color signal. the correction function the correction functions can then be applie d to each pixel value to equalize the response across the image as follows: (eq 1) where p are the pixel values and f is the color dependent correction functions for each color channel. p corrected row, col ?? p sensor row, col ?? f(row, col) ? =
ap0101cs/d rev. 7, 1/16 en 19 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) image flow processor adaptive local tone mapping (altm) real world scenes often have very high dy namic range (hdr) that far exceeds the elec- trical dynamic range of the imager. dynamic range is defi ned as the luminance ratio between the brightest and the darkest object in a scene. in recent years many technolo- gies have been developed to capture the fu ll dynamic range of real world scenes. for example, the multiple exposure method is a widely adopted method for capturing high dynamic range images, which combines a seri es of low dynamic range images of the same scene taken under different exposure times into a single hdr image. even though the new digital imaging technolo gy enables the capture of the full dynamic range, low dynamic range disp lay devices are the limiting factor. today?s typical lcd monitor has contrast ratio around 1,000:1; howe ver, it is not atypical for an hdr image having contrast ratio around 250,000:1. theref ore, in order to repr oduce hdr images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. this is commonly called tone mapping. tone mapping methods can be classified into global to ne mapping and local tone mapping. global tone mapping methods apply the same mapping function to all pixels. while global tone mapping methods provid e computationally simple and easy to use solutions, they often cause loss of contrast and detail. a local tone mapping is thus necessary in addition to glob al tone mapping for the repr oduction of visually more appealing images that also reveal scene deta ils that are important for automotive safety and surveillance applications. local tone mapping methods use a spatially varying mapping function determined by the neighborhood of a pixel, which allows it to increase the local contrast and the visibility of some details of the image. local methods usually yield more pleasing results because they exploit the fact that human vision is more sensitive to local contrast. on semiconductor?s altm solution significan tly improves the perf ormance over global tone mapping. altm is directly applied to the bayer domain to compress the dynamic range from 20-bit to 12-bit. this allows the regular color pipeline to be used for hdr image rendering. color interpolation in the raw data stream fed by th e sensor core to the ifp, each pixel is represented by a 20- or 12-bit integer number, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue, depending on the pixel's position under the color filter array. initial data processing steps, up to and including altm, preserve the one-color-per-pixel nature of the data st ream, but after altm it must be converted to a three-colors-per-pixel stream approp riate for standard color processing. the conversion is done by an edge-sensitive color interpolation module. the module pads the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels . the algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. the edge threshold can be set through register settings. color correction and aperture correction to achieve good color fidelity of the ifp output, interpolated rgb values of all pixels are subjected to color correction. the ifp multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. the three componen ts of the resulting color vector are all sums of three 10-bit numbers. the color co rrection matrix can be either programmed by
ap0101cs/d rev. 7, 1/16 en 20 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) image flow processor the user or automatically selected by th e auto white balance (awb) algorithm imple- mented in the ifp. color correction should ideally produce output colors that are corrected for the spectral sensitivity and co lor crosstalk characteristics of the image sensor. the optimal values of the color co rrection matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. the color correction variables can be adjusted through register settings. to increase image sharpness, a programmable 2d aperture correction (sharpening filter) is applied to color-corrected image data. the gain and threshold for 2d correction can be defined through register settings. gamma correction the gamma correction curve is implemented as a piecewise linear function with 33 knee points, taking 12-bit arguments and mapping th em to 10-bit output. the abscissas of the knee points are fixed at 0, 8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048, 2560, 3072, 3584, and 4096. the 10-bit ordinates are programmable through variables. the ap0101cs has the ability to calculate the 33-point knee points based on the tuning of cam_ll_gamma and cam_ll_contrast_gradie nt_bright. the other method is for the host to program the 33 knee point curve themselves. also included in this block is a fade-to black curve which sets all knee points to zero and causes the image to go black in extreme low light conditions. color kill to remove high-or low-light color artifacts, a co lor kill circuit is included. it affects only pixels whose luminance exceeds a certain preprogrammed threshold. the u and v values of those pixels are attenuated proportionally to the difference between their lumi- nance and the threshold. yuv color filter as an optional processing step, noise suppres sion by one-dimensional low-pass filtering of y and/or uv signals is possible. a 3- or 5-tap filter can be selected for each signal.
ap0101cs/d rev. 7, 1/16 en 21 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) camera control and auto functions camera control and auto functions auto exposure the auto exposure algorithm optimizes scene exposure to minimize clipping and satu- ration in critical areas of the image. this is achieved by controlling exposure time and analog gains of the sensor core as well as digital gains applied to the image. the auto exposure module analyzes image stat istics collected by the exposure measure- ment engine, makes a decision, and programs the sensor and color pipeline to achieve the desired exposure. the measurement engine subdivides the image into 25 windows organized as a 5 x 5 grid. figure 11: 5 x 5 grid ae track driver other algorithm features include the rejection of fast fluctuations in illumination (time averaging), control of speed of response, and control of the sensitivity to small changes. while the default settings are adequate in mo st situations, the user can program target brightness, measurement window, and other parameters described above. the driver changes ae parameters (integrati on time, gains, and so on) to drive scene brightness to the programmable target. to avoid unwanted reaction of ae on smal l fluctuations of scen e brightness or momen- tary scene changes, the ae track driver uses a temporal filter for luma and a threshold around the ae luma target. the driver changes ae parameters only if the difference between the ae luma target and the filtered lu ma is larger than the ae target step and pushes the luma beyond the threshold.
ap0101cs/d rev. 7, 1/16 en 22 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) auto white balance auto white balance the ap0101cs has a built-in awb algorithm de signed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. the algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a driver performi ng the selection of the optimal color correc- tion matrix and ifp digital gain. while defaul t settings of these algorithms are adequate in most situations, the user can reprogram base color correction matrices, place limits on color channel gains, and control the speed of both matrix and gain adjustments. the ap0101cs awb displays the current awb position in color temperature, the range of which will be defined when programming the ccm matrixes. the region of interest can be controlled through the combination of an inclusion window and an exclusion window. dual band ircf for some applications a day/night filter would be switched in/out, this option is an additional cost to the camera system. the ap 0101cs supports the use of dual band ircf, which removes the need for the switching day/ night filter. tuning support is provided for this usage case. refer to the ap0101cs developer guide for details. exposure and white balance modes ap0101cs supports auto and manual exposure and white balance modes. in addition, it will operate within synchronized multi-came ra systems. in this use case, one camera within the system will be the 'master', and the others 'slaves'. the master is used to calculate the appropriate exposu re and white balance. this is then applied to all slaves concurrently under host control. auto mode in auto exposure mode the ae algorithm is responsible for calculating the appropriate exposure to keep the desired scene brightne ss, and for applying the exposure to the underlying hardware. in auto white balance mode the awb algorithm is responsible for calculating the color temperature of the sc ene and applying the appropriate red and blue gains. triggered auto mode the triggered auto exposure and triggered auto white balance modes are intended for the multi-camera use cases, where a host is controlling the exposure and white balance of a number of cameras. the idea is that one camera is in triggered-auto mode (the master), and the others in host-controlled mode (slaves). the master camera must calculate the exposure and gains, the host then copies this to the slaves, and all changes are then applied at the same time. manual mode manual mode is intended to allow simple manual exposure and white balance control by the host. the host needs to set th e cam_aet_exposure_time_ms, cam_aet_ex- posure_gain and cam_awb_color_temper ature controls, the camera will calculate the appropriate integration times and gains.
ap0101cs/d rev. 7, 1/16 en 23 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) flicker avoidance host controlled the host controlled mode is intended to gi ve the host full control over exposure and gains. flicker avoidance flicker occurs when the integration time is not an integer multiple of the period of the light intensity. the ap0101cs can be programm ed to avoid flicker for 50 or 60 hertz. for integration times less than the light intensity period (10ms for 50hz environment), flicker cannot be avoided. the ap0101cs suppor ts an indoor ae mode, that will ensure flicker-free operation. output formatting the ap0101cs can output pixel data as an 8 or 10 bit word, over one or two clocks per pixel. ap0101at supports para llel output & smpte modes. uncompressed ycbcr data ordering the ap0101cs supports swapping ycbcr mode, as illustrated in table 11. the data ordering for the ycbcr output mo des for ap0101cs are shown in table 12 and table 13: note: odd means first cycle; even means second cycle. table 11: ycbcr output data ordering mode data sequence default (no swap) cbi yi cri yi+1 swapped crcb cri yi cbi yi+1 swapped yc yi cbi yi+1 cri swapped crcb, yc yi cri yi+1 cbi table 12: ycbcr output modes (cam _port_parallel_msb_align=0x1, ca m_port_parallel_s wap_bytes = 0, cam_output_format_yuv_swap_red_blue = 0) mode byte pixel i pixel i+1 notes ycbcr_422_8_8 odd (d out [15:8]) cbi cri data range of 0-255 (y=16-235 and c=16-240) even (d out [15:8]) yi yi+1 ycbcr_422_10_10 odd (d out [15:6]) cbi cri data range of 0-1023 (y=64-940 and c=64- 960) even (d out [15:6]) yi yi+1 ycbcr_422_16 single (d out [15:0]) cbi_yi cri_yi+1 data range of 0-255 (y=16-235 and c=16-240) table 13: ycbcr output modes (cam _port_parallel_msb_align=0x0, ca m_port_parallel_s wap_bytes = 0, cam_output_format_yuv_swap_red_blue = 0) mode byte pixel i pixel i+1 notes ycbcr_422_8_8 odd (d out [7 :0]) cbi cri data range of 0-255 (y=16-235 and c=16-240) even (d out [7:0] yi yi+1
ap0101cs/d rev. 7, 1/16 en 24 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) output formatting figure 12: 8- bit ycbcr output (ycbcr_422_8_8) note: cam_port_parallel_msb_align = 0 cam_port_parallel_swap_bytes = 1 cam_output_format_yuv_swap_red_blue = 0 ycbcr_422_10_10 odd (d out [9:0]) cbi cri data range of 0-1023 (y=64-940 and c=64-960)" even (d out [9:0]) yi yi+1 ycbcr_422_16 single (d out [15:0]) cbi_yi cri_yi+1 data range of 0-255 (y=16-235 and c=16-240) table 13: ycbcr output modes (cam _port_parallel_msb_align=0x0, ca m_port_parallel_s wap_bytes = 0, cam_output_format_yuv_swap_red_blue = 0) mode byte pixel i pixel i+1 notes active video y cb y cr y cb y cr y cb y cr ycbycr image image hblank hblank hblank vertical blanking ycbycr vblank image vblank ycbycr image y cb y c r y cb y cr y cb y cr ycbycr image image hblank hblank hblank 00 00 00 00 cr cr cr line valid frame valid pixel clock data[15:8] data[7:0] line valid frame valid pixel clock data[15:8] data[7:0] line valid frame valid pixel clock data[15:8] data[7:0] porch ? 0-255 cycles line valid frame valid pixel clock data[15:8] data[7:0] porch ? 0-255 cycles porch ? 0-255 cycles porch ? 0-255 cycles
ap0101cs/d rev. 7, 1/16 en 25 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) output formatting figure 13: 10-bit ycbcr output (ycbcr_422_10_10) note: cam_port_parallel_msb_align = 1 cam_port_parallel_swap_bytes = 1 cam_output_format_yuv_swap_red_blue = 0 active video y cb y cr y c b y c r y cb y cr ycby cr image image hblank hblank hblank vertical blanking ycbycr vblank image vblank ycb y cr image y cb y cr y cb y c r y cb y cr ycby cr image image hblank hblank hblank 00 00 00 00 cr cr cr line valid frame valid pixel clock data[5:0] data[15:6] line valid frame valid pixel clock data[5:0] data[15:6] line valid frame valid pixel clock data[5:0] data[15:6] line valid frame valid pixel clock data[5:0] data[15:6] porch ? 0-255 cycles porch ? 0-255 cycles porch ? 0-255 cycles porch ? 0-255 cycles
ap0101cs/d rev. 7, 1/16 en 26 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) output formatting figure 14: 16-bit ycbcr output (ycbcr_422_16) note: cam_port_paralle l_swap_bytes = 0 cam_output_format_yuv_swap_red_blue = 0 active video cb cr cb c r cb cr cb c r cb cr cb cr cb cr cb c r image image hblank hblank hblank vertical blanking cbcr cbcr vblank image vblank cbcr cbcr image image image hblank hblank hblank cr cr yyyy yyyy yyyy yyyy y cb cr cb cr cb cr cb c r cb cr cb c r cb cr cb c r cr yy y yyyyy yyyy yyyy y yyyy yyyy y line valid frame valid pixel clock data[7:0] data[15:8] line valid frame valid pixel clock data[7:0] data[15:8] line valid frame valid pixel clock data[7:0] data[15:8] line valid frame valid pixel clock data[7:0] data[15:0] porch ? 0-255 cycles porch ? 0-255 cycles porch ? 0-255 cycles porch ? 0-255 cycles
ap0101cs/d rev. 7, 1/16 en 27 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) output formatting smpte output the data ordering for the smpte output mode for ap0101at is shown in table 14: figure 15: smpte296m output table 14: smpte output mode mode byte pixel i pixel i+1 notes smpte single{dout[15:8],gpio[5:4]}-->cb/cr {dout[7:0],gpio[3:2]} --->y cbi_yi cri_yi+1 data range of 4-1019 (y=64-940 and c=64- 960) active video cb cr cb cr cb cr cb cr 200 cb cr cb cr 3ff 000 000 200 200 3ff 000 000 274 3ff 000 000 200 cb cr cb cr 200 3ff 000 000 274 sav image eav sav image eav hblank hblank blanking blanking blanking hblank sav image eav sav blank vblank eav blank hblank hblank blanking blanking blanking hblank sav blank vblank eav blank sav blank vblank eav blank hblank hblank blanking blanking blanking hblank sav blank vblank eav blank sav image eav hblank hblank blanking blanking blanking hblank blanking yyyy yyyy 040 yyyy 3ff 000 000 200 040 3ff 000 000 274 3ff 000 000 200 yyyy 040 3ff 000 000 274 y y y y y y y y 040 040 3ff 000 000 200 040 000 000 274 000 000 040 000 000 2d8 cb cr cb cr cb cr cb cr 200 200 000 000 200 200 000 000 274 000 000 200 000 000 040 040 040 000 000 040 000 000 000 000 040 000 000 200 200 200 000 000 200 000 000 000 000 2ac 200 000 000 040 040 y y y y 3ff 000 000 2ac 040 3ff 000 000 2d8 3ff 000 000 200 yyyy 040 3ff 000 000 274 200 200 cb cr cb cr 3ff 000 000 2ac 200 3ff 000 000 2d8 3ff 000 000 200 cb cr cb cr 200 3ff 000 000 274 pixel clock data[7:0] gpio3, gpio2 data[15:8] gpio5, gpio4 pixel clock data[7:0] gpio3, gpio2 data[15:8] gpio5, gpio4 pixel clock data[7:0] gpio3, gpio2 data[15:8] gpio5, gpio4 pixel clock data[7:0] gpio3, gpio2 data[15:8] gpio5, gpio4 3ff 3ff 3ff 3ff 3ff 3ff 3ff 2d8 2d8 2d8 2ac 2ac 2ac 3ff 3ff 3ff 3ff 3ff 3ff 3ff 3ff 2ac 2ac 2d8 2d8
ap0101cs/d rev. 7, 1/16 en 28 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) sensor embedded data altm bayer output the data ordering for the altm bayer output modes for ap0101cs are shown in table 15. altm bayer modes ar e selected by setting cam_ mode_select = 7 (altm bayer 12) or 8 (altm bayer 10). table 15 and table 16 show lsb aligned data; it is possible by using a register setting to obtain msb aligned data. the data ordering for the bayer output modes for ap0101cs are shown in table 16. note: raw bayer mode can be selected by setting cam_mode_select = 0x4. sensor embedded data the ap0101cs is capable of passing sensor em bedded data in bayer output mode only. the ap0101cs statistics are avai lable through the serial interface. refer to the developer guide for details. slave two-wire serial interface the two-wire slave serial inte rface bus enables read/write access to control and status registers within the ap0101cs. the interface protocol uses a master/slave model in which a master controls one or more slave devices. protocol data transfers on the two-wire serial inte rface bus are performed by a sequence of low-level protocol elements, as follows: ? a start or restart condition ? a slave address/da ta direction byte ? a 16-bit register address ? an acknowledge or a no-acknowledge bit ?data bytes ? a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start an d stop conditions. table 15: altm bayer output modes mode byte d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 altm_bayer_10single0000 0 0 d9d8d7d6d5d4d3d2d1d0 altm_bayer_12single0000d11d10d9d8d7d6d5d4d3d2d1d0 table 16: bayer output modes mode byte d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 raw_bayer_1 2 single 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
ap0101cs/d rev. 7, 1/16 en 29 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) protocol the s addr pin is used to select between two different addresses in case of conflict with another device. if s addr is low, the slave address is 0x90; if s addr is high, the slave address is 0xba. see table 17 below. the user can change the slave address by changing a register value. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can ge nerate a start conditio n without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/data direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the ap0101cs are 0x90 (write address) and 0x91 (read address). alternate slave addresses of 0xba (write address) and 0xbb (read address) can be selected by asserting the s addr input signal. message byte message bytes are used for sending register ad dresses and register write data to the slave device and for retrieving register read data. the protocol used is outside the scope of the two-wire serial inte rface specification. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to termi- nate a read sequence. table 17: two-wire interface id address switching s addr two-wire interface address id 00x90 10xba
ap0101cs/d rev. 7, 1/16 en 30 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) protocol stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. typical operation a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which a write will take place. this transfer take s place as two 8-bit sequences and the slave sends an acknowledge bit after each sequen ce to indicate that the byte has been received. the master will then transfer the 8-bit or 16-bit data, as one or two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, ju st as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the data transfer is stopped when the master sends a no- acknowledge bit. single read from random location figure 16 shows the typical read cycle of th e host to the ap0101cs. the first two bytes sent by the host are an internal 16-bit regist er address. the following 2-byte read cycle sends the contents of the registers to host. figure 16: single read from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data [15:8] p previous reg address, n reg address, m m+1 a read data [7:0] a
ap0101cs/d rev. 7, 1/16 en 31 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) protocol single read from current location figure 17 shows the single read cycle withou t writing the address. the internal address will use the previous address value written to the register. figure 17: single read from current location sequential read, start from random location this sequence (figure 18) starts in the same way as the single read from random loca- tion (figure 16 on page 30). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 18: sequential read, start from random location sequential read, start from current location this sequence (figure 19) starts in the same way as the single read from current loca- tion (figure 17). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l ? bytes have been read. figure 19: sequential read, start from current location slave address 1 s a read data [15:8] slave address a 1 s p read data [15:8] p previous reg address, n reg address, n+1 n+2 a a read data [7:0] a read data [7:0] a read data (15:8) a a read data (15:8) a read data (7:0) a slave address 0 s sr a reg address[15:8] a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 m+l-2 m+l-1 m+l a p a read data (15:8) a read data (7:0) a read data (15:8) a read data (7:0) a read data (7:0) a a a a a a a read data read data previous reg address, n n+1 n+2 n+l-1 n+l a read data slave address a a 1 a s p read data (15:8) a read data (7:0) a read data (15:8) a read data (7:0) a read data (15:8) a read data (7:0) a read data read data (15:8) a read data (7:0) a aaa aa a
ap0101cs/d rev. 7, 1/16 en 32 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) protocol single write to random location figure 20 shows the typical wr ite cycle from the host to the ap0101cs.the first 2 bytes indicate a 16-bit address of the internal registers with most-significant byte first. the following 2 bytes indicate the 16-bit data. figure 20: single write to random location sequential write, start at random location this sequence (figure 21) starts in the same way as the single write to random location (figure 20). instead of generating a no-acknowl edge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been writte n. the write is terminated by the master generating a stop condition. figure 21: sequential write, start at random location slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+1 a a write data slave address 0 s a reg address[15:8] write data a reg address[7:0] a write data previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a write data write data m+l-2 m+l-1 m+l a a p write data (15:8) write data (7:0) write data (15:8) a write data (7:0) a a a a write data a write data (15:8) a write data (7:0) a write data write data (15:8) a write data (7:0)
ap0101cs/d rev. 7, 1/16 en 33 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) usage modes device configuration and usage modes after power is applied and the device is out of reset (either the power on reset, hard or soft reset), it will enter a boot sequence to configure its operating mode. there are essen- tially three configuration modes: flash/eepr om config, auto config, and host config. the ap0101cs firmware supports a system configuration phase at start-up. this consists of four sub-phases of execution: 1. flash detection, then one of: a. flash config b. auto config c. host config the system configuration phase is entered immediately following power-up or reset. then the firmware performs flash detection. flash detection attempts to detect the pr esence of an spi flash or eeprom device: ? if no device is detected, the firmware then samples the spi_sdi pin state to determine the next mode: ? if spi_sdi is low, then it enters the host-config mode. ? if spi_sdi is high, then it enters the auto-config mode. ? if a device is detected, the firmware switches to the flash-config mode. in the flash-config mode, the firmware in terrogates the device to determine if it contains valid configuration records: ? if no records are detected, then the firmware enters the auto-config mode. ? if records are detected, the firmware processes them. by default, when all flash records are processed the firm ware switches to the host-config mode. however, the records encoded into th e flash can optionally be used to instruct the firmware to proceed to auto-config, or to star t streaming (via a change-config). in the host-config mode, the firmware perf orms no configuration, and remains idle waiting for configuration and commands from the host. the system configuration phase is effectively complete and the ap0101cs will take no actions until the host issues commands. in the auto-config mode, the part will st art streaming with the default settings. usage modes how a camera based on the ap0101cswill be configured depends on what features are used. in the simplest case, an ap0101at oper ating in auto-config mode with no custom- ized settings might be sufficient. in the simplest case no eeprom or flash memory or c is required, as shown in figure 22. figure 22: auto-config mode digital out auto-config mode ap0101cs + image sensor
ap0101cs/d rev. 7, 1/16 en 34 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) host command interface the ap0101cscan be configured by a serial eeprom or flash through the spi interface. figure 23: flash mode figure 24: host mode with flash in this configuration all settings are commu nicated to the ap0101cs and sensor through the microcontroller. figure 25: host mode supported nvm devices the ap0101at supports a variety of spi nv m devices. refer to the flash/eeprom programming section of the developer guide for details. host command interface the ap0101cs has a mechanism to execute higher level commands, the host command interface (hci). once a command has been writ ten through the hci, it will be executed by on-chip firmware and the results are repo rted back. eeprom or flash memory is also available to store commands for later executio n. for details on the host command inter- face and host commands, refer to th e host command interface document. serial eeprom/flash spi ap0101cs + image sensor ap0101cs + image sensor spi 8/16bit c two-wire system bus serial eeprom/flash 8/16bit c two-wire system bus ap0101cs + image sensor
ap0101cs/d rev. 7, 1/16 en 35 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) electrical specifications electrical specifications caution stresses greater than those listed in table 18 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. table 18: absolute maximum ratings symbol parameter rating unit min max v dd _reg digital power (1.8v) -0.3 4.95 v v dd io_h host i/o power (2.5v,3.3v) 2.25 5.4 v v dd io_s sensor i/o power (1.8v, 2.8v) 1.7 5.4 v v dd digital core power 1.1 2.5 v v dd _pll pll power 1.1 2.5 v v dd io_otpm otpm power 2.25 5.4 v v in dc input voltage -0.3 v dd io_*+0.3 v v out dc output voltage -0.3 v dd io_*+0.3 v t stg storage temperature -50 150 c table 19: electrical characteristics and operating conditions parameter condition min typ max unit supply input to on-chip regulator (v dd _reg) 1.62 1.8 1.98 v host io voltage (v dd io_h) 2.25 2.5/3.3 3.6 v sensor io voltage (v dd io_s) 1.7 1.8/2.8 3.1 v core voltage (v dd ) 1.08 1.2 1.32 v pll voltage (v dd _pll) 1.08 1.2 1.32 v otpm power supply (v dd io_otpm) 2.25 2.5/3.3 3.6 v functional operating temperature (ambient - t a ) -30 70 c storage temperature -55 150 c
ap0101cs/d rev. 7, 1/16 en 36 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) electrical specifications figure 26: parallel digital output i/o timing notes: 1. v ih /v il restrictions apply. 2. this is applicable only a when th e pll is bypassed. when the pll is being used then the user should ensure that v ih /v il is met. table 20: ac electrical characteristics (referring to figure 26) default setup conditions: f extclk = 27 mhz, f pixclk = 74.125 mhz or f pixclk = 84 mhz, v dd io_h = v dd _otpm = 2.8v, v dd _reg = v dd io_s = 1.8v, t a = 25c unless otherwise stated symbol parameter conditions min typ max unit notes f extclk external clock frequency 6 30 mhz 1 t r external input clock rise time 10%-90% v dd io_h C 2 5 ns 2 t f external input clock fall time 90%-10% v dd io_h C 2 5 ns 2 d extclk external input clock duty cycle 40 50 60 % t jitter external input clock jitter C 500 C ps f pixclk pixel clock frequency (one-clock/pixel) 6 74.25 mhz pixel clock frequency (two-clocks/pixel) 6 84 mhz t rpixclk pixel clock rise time (10 - 90%) c load =35pf C 3 5 ns t fpixclk pixel clock fall time (10 - 90%) c load =35pf C 3 5 ns t pd pixclk to data valid C 3 5 ns t pfh pixclk to fv high C 3 5 ns t plh pixclk to lv high C 3 5 ns t pfl pixclk to fv low C 3 5 ns t pll pixclk to lv low C 3 5 ns
ap0101cs/d rev. 7, 1/16 en 37 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) electrical specifications notes: 1. vil and vih have min/max limita tions specified by absolute ratings. 2. excludes pins that have internal pu resistors. table 21: dc electric al characteristics symbol parameter condition min max unit notes v ih input high voltage v dd io_h or v dd io_s * 0.8 C v 1 v il input low voltage C v dd io_h or v dd io_s * 0.2 v 1 i in input leakage current v in = 0v or v in = v dd io_h or v dd io_s 10 ? a 2 v oh output high voltage v dd io_h or v dd io_s* 0.80 C v v ol output low voltage C v dd io_h or v dd io_s * 0.2 v table 22: operating current consumption default setup conditions: f extclk = 27 mhz, f pixclk = as below, v dd _reg=1.8v; v dd io_h not included in measurement v dd io_s= 2.8v, v dd io_otpm=3.3v, t a =50c unless otherwise stated symbol conditions min typ max unit v dd _reg 1.62 1.8 1.98 v v dd io_h v dd io_h=2.5v 2.25 2.5 2.75 v v dd io_h=3.3v 3 3.3 3.6 v v dd io_s v dd io_s=1.8v 1.7 1.8 1.9 v v dd io_s=2.8v 2.5 2.8 3.1 v v dd io_otpm v dd io_otpm=2.5v 2.25 2.5 2.75 v v dd io_otpm=3.3v 3 3.3 3.6 v i dd _reg 960p hdr 30 fps 37.125mhz ycbcr_422_16 42 ma 800p hdr 30 fps 84 mhz ycbcr_422_10_10 or ycbcr_422_8_8 36 ma 720p hdr 60 fps 74.25mhz ycbcr_422_16 64 ma 720p hdr 30 fps 37.125mhz ycbcr_422_16 33 ma 720p hdr 30 fps 74.25 mhz ycbcr_422_10_10 or ycbcr_422_8_8 33 ma i dd io_s 960p hdr 30 fps 37.125 mhz ycbcr_422_16 4.4 ma 800p hdr 30 fps 84 mhz ycbcr_422_10_10 or ycbcr_422_8_8 4.3 ma 720p hdr 60 fps74.25 mhz ycbcr_422_16 4.5 ma 720p hdr 30 fps 37.125 mhz ycbcr_422_16 4.3 ma 720p hdr 30 fps 74.25 mhz ycbcr_422_10_10 or ycbcr_422_8_8 4.3 ma i dd io_otpm 960p hdr 30 fps 37.125 mhz ycbcr_422_16 0.25 ma 800p hdr 30 fps 84 mhz ycbcr_422_10_10 or ycbcr_422_8_8 0.25 ma 720p hdr 60 fps 74.25 mhz ycbcr_422_16 0.25 ma 720p hdr 30 fps 37.125 mhz ycbcr_422_16 0.25 ma 720p hdr 30 fps 74.25 mhz ycbcr_422_10_10 or ycbcr_422_8_8 0.25 ma
ap0101cs/d rev. 7, 1/16 en 38 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) electrical specifications total power consumption 1 960p hdr 30 fps 37.125 mhz ycbcr_422_16 89 mw 800p hdr 30 fps 84 mhz ycbcr_422_10_10 or ycbcr_422_8_8 77 mw 720p hdr 60 fps 74.25 mhz ycbcr_422_16 129 mw 720p hdr 30 fps 37.125 mhz ycbcr_422_16 72 mw 720p hdr 30 fps 74.25 mhz ycbcr_422_10_10 or ycbcr_422_8_8 71 mw table 23: standby current consumption f extclk = 27 mhz, v dd _reg =1.8v, v dd io_s=1.8v,v dd io_otpm=v dd io_h=3.3v, ta = 50c, excludes v dd io_h current symbol parameter condition typ max unit hard standby total standby current when asserting the standby signal 1.6 ma standby power 2.9 mw soft standby (clock on) total standby current f extclk = 27 mhz 2.1 ma standby power 3.8 mw table 24: inrush current supply max. current v dd _reg (1.8v) 150ma v dd io_h (2.5/3.3v) 80ma v dd io_s (2.8v/1.8v) 110ma v dd io_otpm (2.5/3.3v) 170ma table 22: operating current consumption (continued) default setup conditions: f extclk = 27 mhz, f pixclk = as below, v dd _reg=1.8v; v dd io_h not included in measurement v dd io_s= 2.8v, v dd io_otpm=3.3v, t a =50c unless otherwise stated symbol conditions min typ max unit
ap0101cs/d rev. 7, 1/16 en 39 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) two-wire serial register interface two-wire serial register interface the electrical characte ristics of the slave two-wire serial register interface (sclk, sdata) are shown in figure 27 and table 25. figure 27: slave two-wire seria l bus timing parameters (ccis) notes: 1. all values referred to vihmin = 0.9 v dd and vilmax = 0.1v dd levels. sensor exclk = 27 mhz. 2. a device must internally provide a ho ld time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 3. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the s clk signal. 4. cb = total capacitance of one bus line in pf. the electrical characteristics of the master two-wire serial register interface (m_s clk , m_s data ) are shown in figure 28 and table 26. table 25: slave two-wire serial bus characteristics (ccis) default setup conditions: f extclk = 27 mhz, f pixclk = 74.125 mhz, v dd io_h = v dd _otpm = 2.8v, v dd _reg = v dd io_s = 1.8v, tj = 25c unless otherwise stated parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the s clk clock t low 4.7 - 1.3 - ? s high period of the s clk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time t hd;dat 0 2 3.45 3 00.9 3 ? s data set-up time t su;dat 250 - 100 - ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 4 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 4 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance c in_si - 3.3 - 3.3 pf s data max load capacitance c load_sd - 30 - 30 pf s data pull-up resistor r sd 1.5 4.7 1.5 4.7 k ? s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
ap0101cs/d rev. 7, 1/16 en 40 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) two-wire serial register interface figure 28: master two-wire ser ial bus timing parameters (ccim) notes: 1. all values referred to vihmin = 0.9 v dd and vilmax = 0.1v dd levels. sensor exclk = 27 mhz. 2. a device must internally provide a hold time of at least 300 ns for the m_s data signal to bridge the undefined region of the falling edge of m_s clk . 3. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the m_s clk signal. 4. cb = total capacitance of one bus line in pf. table 26: master two- wire serial bus characteristics (ccim) default setup conditions: f extclk = 27 mhz, f pixclk = 74.125 mhz, v dd io_h = v dd _otpm = 2.8v, v dd _reg = v dd io_s = 1.8v, tj = 25c unless otherwise stated parameter symbol standard-mode fast-mode unit min max min max m_s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the m_s clk clock t low 4.7 - 1.2 - ? s high period of the m_s clk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time t hd;dat 0 2 3.45 3 00.9 3 ? s data set-up time t su;dat 250 - 100 - ns rise time of both m_s data and m_s clk signals t r - 1000 20 + 0.1cb 4 300 ns fall time of both m_s data and m_s clk signals t f - 300 20 + 0.1cb 4 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance c in_si - 3.3 - 3.3 pf m_s data max load capacitance c load_sd - 30 - 30 pf m_s data pull-up resistor r sd 1.5 4.7 1.5 4.7 k ? s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
ap0101cs/d rev. 7, 1/16 en 41 ?semiconductor components industries, llc,2016. ap0101cs hdr: image signal processor (isp) package and die options package and die options figure 29: package diagram vfbga81 6.5x6.5 case 138ag issue o date 30 dec 201 4
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